The present invention relates to semiconductor devices and methods off making semiconductor devices, and more particularly low voltage integrated circuit semiconductor devices and methods in which JFETs are formed in the same steps that are used to form complementary bipolar transistors.
Low voltage, integrated circuit semiconductor devices with bipolar transistors may desirably include JFETs to perform such functions as low input current and analog switching, and multiplexing. NJFETs are usually preferred because they provide higher transconductance and lower resistance than P type devices of comparable size due to the higher mobility of electrons than holes.
The manufacture of integrated circuit semiconductor devices involves a multiplicity of complex sides that are desirably combined or eliminated to reduce manufacturing cost and complexity. As is known, some steps in the manufacture of bipolar transistors for integrated circuits can be used to form parts of other components. Combined steps may be used to advantage to provide components that have particularly well matched operating characteristics. When PNP and NPN bipolar transistors are formed in the same steps, the process is known as a complementary bipolar process and the transistors so made are denominated complementary bipolar transistors. See, for example, U.S. Pat. No. 4,969,823 issued Nov. 13, 1990 to Lapham, et al. in which complementary bipolar transistors are formed by doping adjacent areas of a semiconductor substrate to form two areas of opposite conductivity type, growing an epitaxial layer on the substrate, and up-diffusing the dopant from the substrate into the epitaxial layer so as to create collector regions for complementary NPN and PNP transistors. However, there is no suggestion how the disclosed process may form a JFET at the same time.
Parts of relatively high voltage JFETs (pinch off voltages of more than 20 volts) have been formed in the same steps used to form complementary bipolar transistors, but the same steps have not been used to form low voltage JFETs for signal processing and analog switching applications that require a pinch off voltage of less than 5 volts. A 5 volt pinch-off voltage is about as large as can be used in signal processors and analog switches that use .+-.15 volts power supplies, in which signal swings are typically 5 volts from supply voltage. These low voltage JFETs have smaller, and more critical dimensions than high voltage JFETs. For example, U.S. Pat. No. 4,729,008 issued Mar. 1, 1988 to the inventor hereof, suggests that a high voltage JFET may have its source and drain, channel and a top gate formed in steps used to make complementary vertical bipolar transistors. However, it does not suggest how to use common steps when the JFET and transistors being formed have critical dimensions that do not match.
Of particular note are the conflicts between (a) the desired vertical distances in the collector of the transistors and the channel of the JFET, and (b) the doping levels therein. As will become apparent, these conflicts arise because the collectors of the transistors and channel of JFET are to be formed in the same steps.
An important characteristic of a JFET is its pinch-off voltage Vp. JFETs are designed to have a particular Vp that may vary within a specified range. Vp is determined by the doping level and the thickness of the channel between the top and bottom gates. For example, when the top and bottom gates are more heavily doped than the channel (so that the two gate-channel junctions can be modeled as one-sided step junctions), pinch-off voltage is: EQU Vp={[qN.sub.D (0.5t).sup.2 ]/(2.epsilon..sub.SI .epsilon..sub.0)}-.PHI..sub.B ( 1)
where,
q is electron charge, PA1 N.sub.D is channel doping concentration, PA1 t is channel thickness, PA1 .epsilon..sub.SI is relative dielectric constant of silicon, PA1 .epsilon..sub.0 is dielectric constant of free space, PA1 .PHI..sub.B is the PN junction built-in voltage.
For pinch-off voltages of less than 5 volts, the sensitivity to changes in channel doping and thickness is apparent. For example, if channel doping is too high, the channel thickness will need to be too thin to be manufacturable using current techniques.
This sensitivity is particularly vexing because channel doping and thickness vary during manufacture and are very difficult to control to the precision needed. Recent developments in semiconductor device manufacturing methods permit channel doping to be controlled to within about .+-.10% and channel thickness to within about .+-.5% for epitaxially grown channels.
There are also operational characteristics of bipolar transistors that should be considered when JFETs are to be made in the same steps. It is particularly desirable to reduce transistor collector resistance and to achieve a desired breakdown voltage, usually Bvceo. These characteristics may be controlled by controlling the vertical distance between the bottom of the transistor base and the heavily doped part of the lower collector layer. This distance should be large enough so that a depletion layer that extends down from the base when the transistor is operating does not contact the lower collector layer before the desired breakdown voltage is achieved. However, because collector resistance increases as this distance increases, the distance desirably is not much greater than that needed for the desired breakdown voltage in order to minimize collector resistance.
Thus, the vertical distances defining the channel thickness and the distance between base and lower collector layer are to be specifically set, and since they are to be formed in the same steps (as will be discussed below) are desirably the same. Further, the doping levels in these areas are also to be specifically set in the same steps and thus are also desirably the same. These objectives have not been achieved in the prior art.
Accordingly, it is an object of the present invention to provide a novel semiconductor device with a JFET and complementary bipolar transistors and method of making the device that obviate the problems of the prior art.
It is another object of the present invention to provide a novel semiconductor device with a JFET and complementary bipolar transistors and method of making the device in which the bottom gate of the of the JFET and the lower collector layer are formed in the same steps.
It is yet another object of the present invention to provide a novel semiconductor device with a JFET and complementary bipolar transistors formed in the same steps in which the pinch-off voltage of the JFET and breakdown voltage of the transistors are sufficient for low voltage operation.
It is still another object of the present invention to provide a novel semiconductor device with a JFET and complementary bipolar transistors formed in the same steps in which the distances between base and lower collector layer in the two transistors are separately controllable, with one of the distances being the same as the channel thickness in the JFET.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of preferred embodiments.